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@simten/mcp

GitHub Actions Scanned 15h ago

MCP server for Simten. Live circuit simulation with real-time browser push via WebSocket.

npm
D
56.1 / 100

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PermissionsTool SafetyAuthAnnotationsCode QualityStabilitySpecVuln HistoryAuthorTransparencyCommunity

Tools 8

simulate_circuit
annotations: none low

Compile and simulate a circuit and return signal traces + steady-state cycle. OBSERVATION ONLY — this shows what the circuit does, NOT whether it is correct; use verify_circuit to establish correctness. Does not touch the browser canvas unless show:true. Canvas policy: do not paint during tight iteration; paint at a verify tier-pass, or for a specific failure worth inspecting (pass show:true with a reason).

source string filePath string
get_grammar
annotations: none low

Return the circuit-builder API: how to write a `circuit()` module — inputs/outputs, nodes, connect — with worked examples. Call this before writing a circuit.

list_components
annotations: none low

Return the full catalog of available components from `@simten/core/std`, each with its ports and constructor options (e.g. `Register({ width })`). Call this to discover exact part names and parameters instead of guessing.

get_verify_api
annotations: none low

Return how to write a `.verify.ts` testbench for `verify_circuit`: the `simulate()` stepper API (set/tick/get/dispose), `verify.exhaustive` vs `verify.check`, `declareOracle`, and worked examples (incl. the Tier-A npm-oracle pattern). Call this before writing a testbench.

run_on_fpga
annotations: none low

Build, flash, and UART-capture a project on a connected ULX3S FPGA. Known projects at the time of writing: cpu (RV32I CPU, requires firmware), snake (HDMI hardware Snake), uart_test (standalone UART). New projects can be added by dropping a descriptor in hardware/ulx3s/projects/ and registering it in projects/index.ts — they become callable here without editing this tool. The CLI will reject unknown names with a clear error listing what is registered. Returns a structured RunResult covering every stage (compile, synth, flash, run, match). Kills any active picocom before flashing.

check_circuit
annotations: none low

Parse and validate circuit source code. Returns structured diagnostics including errors, warnings, and suggestions. Runs the full 4-phase validation pipeline: syntax, semantic, type, and structural checks.

source string filePath string
show_circuit
annotations: none low

Paint or update the live circuit canvas in the browser — the only tool that draws. This is the ONLY thing that updates the canvas: editing the .circuit.ts file does NOT auto-update the browser, so re-call show_circuit (typically after a verify tier-pass) to repaint. Call with NO source/filePath to list connected browser tabs (discovery). Pass close:true to close the preview and stop the server. Canvas policy: don

close boolean source string
read_waveform
annotations: none low

Query a VCD waveform file (from iverilog cross-validation runs or other simulators) for specific signals over a cycle window. Returns transitions or per-cycle values in a token-efficient shape. Use test_name (e.g.

Permissions 4

network medium
Server uses network capabilities via: fetch()
filesystem low
Server uses filesystem capabilities via: fs
shell high
Server uses shell capabilities via: child_process, execSync(), spawn(), spawnSync()
env_vars low
Server uses env_vars capabilities via: process.env

Scan Findings 49

low
Tool 'simulate_circuit' has no annotations annotation_checker · 100%
low
Tool 'get_grammar' has no annotations annotation_checker · 100%
low
Tool 'list_components' has no annotations annotation_checker · 100%
low
Tool 'get_verify_api' has no annotations annotation_checker · 100%
low
Tool 'run_on_fpga' has no annotations annotation_checker · 100%
low
Tool 'check_circuit' has no annotations annotation_checker · 100%
low
Tool 'show_circuit' has no annotations annotation_checker · 100%
low
Tool 'read_waveform' has no annotations annotation_checker · 100%
medium
OAuth implementation without PKCE auth_checker · 75%
info
Sandbox failed to start for behavioral verification behavioral_verifier · 100%
medium
Excessive dependency count: 93 direct dependencies dependency_analyzer · 90%
medium
Suspicious package name: react-dom dependency_analyzer · 60%
medium
Suspicious package name: react-markdown dependency_analyzer · 60%
medium
Vulnerable dependency: vitest@4.1.8 (GHSA-82fw-gwwq-j7x9) dependency_analyzer · 95%
medium
Vulnerable dependency: hono@4.12.34 (GHSA-crvj-82cr-hjcx) dependency_analyzer · 95%
medium
Vulnerable dependency: hono@4.12.34 (GHSA-g6gw-c38x-mqfc) dependency_analyzer · 95%
medium
Vulnerable dependency: hono@4.12.34 (GHSA-gqvv-2mrq-wpjv) dependency_analyzer · 95%
medium
Vulnerable dependency: @modelcontextprotocol/sdk@1.12.0 (GHSA-345p-7cg4-v4c7) dependency_analyzer · 95%
medium
Vulnerable dependency: @modelcontextprotocol/sdk@1.12.0 (GHSA-8r9q-7v3j-jr4g) dependency_analyzer · 95%
medium
Vulnerable dependency: @modelcontextprotocol/sdk@1.12.0 (GHSA-w48q-cv73-mx4w) dependency_analyzer · 95%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/hardware/ulx3s/lib/pipeline.ts:126 entropy_analyzer · 75%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/hardware/ulx3s/lib/pipeline.ts:174 entropy_analyzer · 75%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/hardware/ulx3s/projects/cpu/verify.ts:42 entropy_analyzer · 75%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/hardware/ulx3s/projects/cpu/index.ts:78 entropy_analyzer · 75%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/hardware/ulx3s/projects/cpu/cycle-diff.ts:288 entropy_analyzer · 75%
medium
High-entropy string (6.44 bits/char) in simtenHQ-simten-b26d453/packages/ui/src/editor/lib/visualization/vcd-generator.ts:114 entropy_analyzer · 61%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/packages/core/src/verilog/__tests__/snake.build.test.ts:60 entropy_analyzer · 75%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/packages/core/src/verilog/__tests__/counter.build.test.ts:89 entropy_analyzer · 75%
medium
Buffer.from base64 in simtenHQ-simten-b26d453/packages/core/src/verilog/__tests__/alu.build.test.ts:77 entropy_analyzer · 75%
info
package.json metadata manifest_parser · 100%
info
Tool: simulate_circuit manifest_parser · 70%
info
Tool: get_grammar manifest_parser · 70%
info
Tool: list_components manifest_parser · 70%
info
Tool: get_verify_api manifest_parser · 70%
info
Tool: run_on_fpga manifest_parser · 70%
info
Tool: check_circuit manifest_parser · 70%
info
Tool: show_circuit manifest_parser · 70%
info
Tool: read_waveform manifest_parser · 70%
info
Transport: stdio manifest_parser · 90%
info
Required env vars (20) manifest_parser · 80%
info
Sandbox failed to start for output poisoning scan output_poisoning · 100%
medium
Permission: network access detected permission_analyzer · 70%
low
Permission: filesystem access detected permission_analyzer · 90%
high
Permission: shell access detected permission_analyzer · 95%
low
Permission: env_vars access detected permission_analyzer · 90%
critical
Tool poisoning in 'get_grammar': Cross-tool sequencing directive poisoning · 85%
critical
Tool poisoning in 'get_verify_api': Cross-tool sequencing directive poisoning · 85%
info
SBOM generated: 98 components sbom_generator · 100%
medium
No build provenance detected (SLSA L0) slsa_assessor · 90%